A CMOS imager circuit includes a focal plane array of pixel circuits, each one of the pixels including a photosensor, for example, a photogate, photoconductor or a photodiode overlying a substrate for accumulating photo-generated charge in the underlying portion of the substrate. Each pixel has a readout circuit that includes at least an output field effect transistor formed in the substrate and a charge storage region formed on the substrate connected to the gate of an output transistor. The charge storage region may be constructed as a floating diffusion region. Each pixel may include at least one electronic device such as a transistor for transferring charge from the photosensor to the storage region and one device, also typically a transistor, for resetting the storage region to a predetermined charge level prior to charge transference.
In a CMOS imager, the active elements of a pixel perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) resetting the storage region to a known state; (4) transfer of charge to the storage region; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing photo charge. Photo charge may be amplified when it moves from the initial charge accumulation region to the storage region. The charge at the storage region is typically converted to a pixel output voltage by a source follower output transistor.
CMOS imagers of the type discussed above are generally known as discussed, for example, in U.S. Pat. Nos. 6,140,630, 6,376,868, 6,310,366, 6,326,652, 6,204,524 and 6,333,205, assigned to Micron Technology, Inc., which are hereby incorporated by reference in their entirety.
FIG. 1 illustrates a CMOS imager 100 having a pixel array 102 connected to column sample and hold (S/H) circuitry 136. The pixel array 102 comprises a plurality of pixels 220 arranged in a predetermined number of rows and columns.
A plurality of row and column lines are provided for the entire array 102. The row lines e.g., SEL(0) are selectively activated by row decoder 130 and driver circuitry 132 in response to an applied row address to apply pixel operating row signals. Column select lines (not shown) are selectively activated in response to an applied column address by column circuitry that includes column decoder 134. Thus, row and column addresses are provided for each pixel 220. The CMOS imager 100 is operated by a sensor control and image processing circuit 150, which controls the row and column circuitry for selecting the appropriate row and column lines for pixel readout and which could perform other processing functions. Additionally, voltage supply circuit 144 provides a pixel supply voltage, Vaa_pix, to the pixels in the array.
Pixels in each column of the pixel array are connected to sampling capacitors and switches in the S/H circuitry 136. A pixel reset signal Vrst and a pixel image signal Vsig for selected pixels are sampled and held by the S/H circuitry 136. A differential signal (Vrst-Vsig) is produced for each readout pixel by the differential amplifier 138 (AMP), which may also apply a gain to the signal received from the S/H circuitry 136. The differential signal is digitized by an analog-to-digital converter 140. The analog-to-digital converter 140 supplies the digitized pixel signals to the sensor control and image processing circuit 150, which among other things, forms a digital image output.
FIG. 2 illustrates a portion 210 of CMOS imager 100. The illustrated portion 210 includes a pixel 220 connected to a column sample and hold circuit 240 by a pixel output column line 232. The portion 210 also shows the differential amplifier 138 and analog-to-digital converter 140.
The illustrated pixel 220 includes a photosensor 222 (e.g., a pinned photodiode, photogate, etc.), transfer transistor 224, floating diffusion region FD, reset transistor 226, source follower transistor 228 and row select transistor 230. The photosensor 222 is connected to the floating diffusion region FD by the transfer transistor 224 when the transfer transistor 224 is activated by a transfer control signal TX. The reset transistor 226 is connected between the floating diffusion region FD and the array pixel supply voltage Vaa_pix. A reset control signal RST is used to activate the reset transistor 226, which resets the floating diffusion region FD (as is known in the art).
The source follower transistor 228 has its gate connected to the floating diffusion region FD and is connected between the array pixel supply voltage Vaa_pix and the row select transistor 230. The source follower transistor 228 converts the stored charge at the floating diffusion region FD into an electrical output voltage signal. The row select transistor 230 is controllable by a row select signal SEL for selectively connecting the source follower transistor 228 and its output voltage signal to the pixel output line 232.
The column sample and hold circuit 240 includes a bias transistor 256, controlled by a control voltage Vln_bias, that is used to bias the pixel output line 232. The pixel output line 232 is also connected to a first capacitor 244 thru a sample and hold reset signal switch 242. The sample and hold reset signal switch 242 is controlled by the sample and hold reset control signal SHR. The pixel output line 232 is also connected to a second capacitor 254 thru a sample and hold pixel signal switch 252. The sample and hold pixel signal switch 252 is controlled by the sample and hold pixel control signal SHS. The switches 242, 252 are typically MOSFET transistors.
A second terminal of the first capacitor 244 is connected to the amplifier 138 via a first column select switch 250, which is controlled by a column select signal COLUMN_SELECT. The second terminal of the first capacitor 244 is also connected to a clamping voltage Vcl via a first clamping switch 246. Similarly, the second terminal of the second capacitor 254 is connected to the amplifier 138 by a second column select switch 260, which is controlled by the column select signal COLUMN_SELECT. The second terminal of the second capacitor 254 is also connected to the clamping voltage Vcl by a second clamping switch 248.
The clamping switches 246, 248 are controlled by a clamping control signal CLAMP. As is known in the art, the clamping voltage Vcl is used to place a charge on the two capacitors 244, 254 when it is desired to store the reset and pixel signals, respectively (when the appropriate sample and hold control signals SHR, SHS are also generated).
Referring to FIGS. 2 and 3, in operation, the row select signal SEL is driven high, which activates the row select transistor 230. When activated, the row select transistor 230 connects the source follower transistor 228 to the pixel output line 232. The clamping control signal CLAMP is then driven high to activate the clamping switches 246, 248, allowing the clamping voltage Vcl to be applied to the second terminal of the sample and hold capacitors 244, 254. The reset signal RST is then pulsed to activate the reset transistor 226, which resets the floating diffusion region FD. The signal from the source follower 228 (based on the reset floating diffusion region FD) is then sampled when the sample and hold reset control signal SHR is pulsed. At this point, the first capacitor 244 stores the pixel reset signal Vrst.
Afterwards, the transfer transistor control signal TX is pulsed, causing charge from the photosensor 222 to be transferred to the floating diffusion region FD. The signal from the source follower 228 (based on the charge transferred to the floating diffusion region FD) is sampled when the sample and hold pixel control signal SHS is pulsed. At this point, the second capacitor 254 stores a pixel image signal Vsig. A differential signal (Vrst-Vsig) is produced by the differential amplifier 138. The differential signal is digitized by the analog-to-digital converter 140. The analog-to-digital converter 140 supplies the digitized pixel signals to the processor 150.
When designing imagers and products incorporating them, it is desirable to know the gain of the source follower transistors 228 in the pixels 220. For example, designers use this gain value when calculating the conversion gain and the floating diffusion responsivity of the pixels 220 in an array 102 and when comparing outputs of imagers made using different processes. Currently, there is no direct way to measure the gain of the source follower transistors 228 accurately. Instead, designers use an approximate value of the source follower gain, such as 0.8. There exists a need and desire for a technique for directly measuring the gain of the source follower transistors 228 used in imager pixels 220.